STP5N30 STP5N30fi n - channel enhancement mode power mos transistor n typical r ds(on) = 1.2 w n avalanche rugged technology n 100% avalanche tested n repetitive avalanche data at 100 o c n application oriented characterization applications n high speed switching n switch mode power supplies (smps) n chopper regulators, converters, motor control, lighting for industrial and consumer environment n particularly suitable for electronic fluorescent lamp ballasts internal schematic diagram type v dss r ds(on) i d STP5N30 STP5N30fi 300 v 300 v < 1.4 w < 1.4 w 5 a 3.5 a 1 2 3 to-220 isowatt220 december 1996 absolute maximum ratings symbol parameter value unit STP5N30 STP5N30fi v ds drain-source voltage (v gs = 0) 300 v v dgr drain- gate voltage (r gs = 20 k w )300v v gs gate-source voltage 20 v i d drain current (continuous) at t c = 25 o c53.5a i d drain current (continuous) at t c = 100 o c3.2 2.2a i dm ( ) drain current (pulsed) 20 20 a p tot total dissipation at t c = 25 o c7535w derating factor 0.6 0.28 w/ o c v iso insulation withstand voltage (dc) ? 2000 v t stg storage temperature -65 to 150 o c t j max. operating junction temperature 150 o c ( ) pulse width limited by safe operating area 1 2 3 1/10
thermal data to-220 isowatt220 r thj-case thermal resistance junction-case max 1.67 3.57 o c/w r thj-amb r thc-sink t l thermal resistance junction-ambient max thermal resistance case-sink typ maximum lead temperature for soldering purpose 62.5 0.5 300 o c/w o c/w o c avalanche characteristics symbol parameter max value unit i ar avalanche current, repetitive or not-repetitive (pulse width limited by t j max, d < 1%) 5a e as single pulse avalanche energy (starting t j = 25 o c, i d = i ar , v dd = 50 v) 50 mj e ar repetitive avalanche energy (pulse width limited by t j max, d < 1%) 1.5 mj i ar avalanche current, repetitive or not-repetitive (t c = 100 o c, pulse width limited by t j max, d < 1%) 3.2 a electrical characteristics (t case = 25 o c unless otherwise specified) off symbol parameter test conditions min. typ. max. unit v (br)dss drain-source breakdown voltage i d = 250 m a v gs = 0 300 v i dss zero gate voltage drain current (v gs = 0) v ds = max rating v ds = max rating x 0.8 t c = 125 o c 10 100 m a m a i gss gate-body leakage current (v ds = 0) v gs = 20 v 100 na on ( * ) symbol parameter test conditions min. typ. max. unit v gs(th) gate threshold voltage v ds = v gs i d = 250 m a 234v r ds(on) static drain-source on resistance v gs = 10v i d = 2.5 a 1.2 1.4 w i d(on) on state drain current v ds > i d(on) x r ds(on)max v gs = 10 v 5a dynamic symbol parameter test conditions min. typ. max. unit g fs ( * )forward transconductance v ds > i d(on) x r ds(on)max i d = 2.5 a 2 3.1 s c iss c oss c rss input capacitance output capacitance reverse transfer capacitance v ds = 25 v f = 1 mhz v gs = 0 500 80 16 700 110 25 pf pf pf STP5N30/fi 2/10
electrical characteristics (continued) switching on symbol parameter test conditions min. typ. max. unit t d(on) t r turn-on time rise time v dd = 150 v i d = 2.5 a r g = 50 w v gs = 10 v (see test circuit, figure 3) 45 30 60 40 ns ns (di/dt) on turn-on current slope v dd = 240 v i d = 5 a r g = 50 w v gs = 10 v (see test circuit, figure 5) 330 a/ m s q g q gs q gd total gate charge gate-source charge gate-drain charge v dd = 240 v i d = 5 a v gs = 10 v 20 6 8 30 nc nc nc switching off symbol parameter test conditions min. typ. max. unit t r(voff) t f t c off-voltage rise time fall time cross-over time v dd = 240 v i d = 5 a r g = 50 w v gs = 10 v (see test circuit, figure 5) 35 20 60 50 30 80 ns ns ns source drain diode symbol parameter test conditions min. typ. max. unit i sd i sdm ( ) source-drain current source-drain current (pulsed) 5 20 a a v sd ( * ) forward on voltage i sd = 5 a v gs = 0 1.6 v t rr q rr i rrm reverse recovery time reverse recovery charge reverse recovery current i sd = 5 a di/dt = 100 a/ m s v dd = 100 v t j = 150 o c (see test circuit, figure 5) 300 1.7 13 ns m c a ( * ) pulsed: pulse duration = 300 m s, duty cycle 1.5 % ( ) pulse width limited by safe operating area safe operating areas for to-220 safe operating areas for isowatt220 STP5N30/fi 3/10
thermal impedeance for to-220 derating curve for to-220 output characteristics thermal impedance for isowatt220 derating curve for isowatt220 transfer characteristics STP5N30/fi 4/10
transconductance static drain-source on resistance gate charge vs gate-source voltage capacitance variations normalized on resistance vs temperature normalized gate threshold voltage vs temperature STP5N30/fi 5/10
turn-on current slope turn-off drain-source voltage slope cross-over time switching safe operating area accidental overload area source-drain diode forward characteristics STP5N30/fi 6/10
fig. 2: unclamped inductive waveforms fig. 3: switching times test circuits for resistive load fig. 4: gate charge test circuit fig. 5: test circuit for inductive load switching and diode reverse recovery time fig. 1: unclamped inductive load test circuits STP5N30/fi 7/10
dim. mm inch min. typ. max. min. typ. max. a 4.40 4.60 0.173 0.181 c 1.23 1.32 0.048 0.051 d 2.40 2.72 0.094 0.107 d1 1.27 0.050 e 0.49 0.70 0.019 0.027 f 0.61 0.88 0.024 0.034 f1 1.14 1.70 0.044 0.067 f2 1.14 1.70 0.044 0.067 g 4.95 5.15 0.194 0.203 g1 2.4 2.7 0.094 0.106 h2 10.0 10.40 0.393 0.409 l2 16.4 0.645 l4 13.0 14.0 0.511 0.551 l5 2.65 2.95 0.104 0.116 l6 15.25 15.75 0.600 0.620 l7 6.2 6.6 0.244 0.260 l9 3.5 3.93 0.137 0.154 dia. 3.75 3.85 0.147 0.151 l6 a c d e d1 f g l7 l2 dia. f1 l5 l4 h2 l9 f2 g1 to-220 mechanical data p011c STP5N30/fi 8/10
dim. mm inch min. typ. max. min. typ. max. a 4.4 4.6 0.173 0.181 b 2.5 2.7 0.098 0.106 d 2.5 2.75 0.098 0.108 e 0.4 0.7 0.015 0.027 f 0.75 1 0.030 0.039 f1 1.15 1.7 0.045 0.067 f2 1.15 1.7 0.045 0.067 g 4.95 5.2 0.195 0.204 g1 2.4 2.7 0.094 0.106 h 10 10.4 0.393 0.409 l2 16 0.630 l3 28.6 30.6 1.126 1.204 l4 9.8 10.6 0.385 0.417 l6 15.9 16.4 0.626 0.645 l7 9 9.3 0.354 0.366 ? 3 3.2 0.118 0.126 l2 a b d e h g l6 ? f l3 g1 123 f2 f1 l7 l4 isowatt220 mechanical data p011g STP5N30/fi 9/10
information furnished is believed to be accurate and reliable. however, sgs-thomson microelectronics assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. no license is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelectronics. specification s mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously s upplied. sgs-thomson microelectronics products are not authorized for use as critical components in life support devices or systems with out express written approval of sgs-thomson microelectonics. ? 1996 sgs-thomson microelectronics - printed in italy - all rights reserved sgs-thomson microelectronics group of companies australia - brazil - canada - china - france - germany - hong kong - italy - japan - korea - malaysia - malta - morocco - the n etherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a . STP5N30/fi 10/10
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